1. Field of the Invention
This invention relates generally to memory devices, and more particularly, to a memory device having simultaneously accessible tag and data arrays.
2. Description of the Related Art
In many computer systems high speed, redundant memories have been used to store recently used or anticipated use data. The memories are referred to as cache memories. A cache memory mirrors data stored in the main memory of the computer system, but because of its significantly higher speed, cache data may can be retrieved quickly. Typically, dynamic random access memories (DRAM) are used as main memory devices due to their high density. Cache memories are typically static random access memories (SRAM). SRAMs have a lower density than DRAMs, but they are significantly faster.
One type of SRAM is a synchronous burst SRAM. This type of SRAM includes a burst counter for generating internal addresses to sequentially access a plurality of cells in the SRAM. These internal addresses may be generated, and the sequential cells may be accessed more quickly than if the SRAM were to be externally addressed. Typically these burst accesses may access four or eight internal accesses.
Data is organized in a cache using tag and data arrays. The data array stores the redundant data corresponding to data stored in the main memory. The tag array stores identifying information to cross-reference the cache data stored in the data array to the main memory data. The tag array also stores status information regarding the status of the cache data (e.g., the cache data is valid or invalid, the cache data has been updated without having been written to the main memory, etc.).
While burst accesses do provide quicker access to the cache data, they also have at least one drawback in that the tag array cannot be accessed during the burst. For example, consider that an eight cycle burst is in progress, and the cache receives a subsequent request for a tag lookup to determine if certain data is stored in the data array. The cache must wait for the burst access to complete before the tag lookup can commence. If the tag lookup misses (i e., the data is not present in the cache), the computer system must then issue a request to retrieve the data from the main memory, a relatively slow process. Waiting for the burst access to complete adds additional latency to the operation of the cache. As the length of burst accesses increases, corresponding to larger cache sizes, the latency problem is exacerbated.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a memory device including a data array, a tag array, and control logic. The data array is adapted to store a plurality of data array entries. The tag array is adapted to store a plurality of data array entries corresponding to the data array entries. The control logic adapted to access a subset of the data array entries in the data array using a burst access and to access the tag array during the burst access.
Another aspect of the present invention is seen in a method for accessing a memory device. The memory device includes a data array and a tag array. The method includes receiving a data array burst access command. The data array is accessed in response to the data array burst access command. A tag array access is received. The tag array is accessed in response to the tag array access command while the data array is being accessed.